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Modeling digital crosstalk

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Jay Barracato:
So I set out to demo digital crosstalk for my DE students. Basically, I applied a signal to two different circuits with a load resistor.

I modeled the capacitance of parallel signal wires with a small capacitor.

The first photo shows the breadboard, the second is the square wave signal with the crosstalk. The third photo is the result of slowing the input down by switching to the triangular wave.

For the record, the spikes in the square waveform are large enough to cause digital errors in the data.


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Jay Barracato:

--- Quote from: Jay Barracato on April 16, 2019, 04:56:28 pm ---So I set out to demo digital crosstalk for my DE students. Basically, I applied a signal to two different circuits with a load resistor.

I modeled the capacitance of parallel signal wires with a small capacitor.

The first photo shows the breadboard, the second is the square wave signal with the crosstalk. The third photo is the result of slowing the input down by switching to the triangular wave.

For the record, the spikes in the square waveform are large enough to cause digital errors in the data.


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--- End quote ---
Then a replaced the capacitor with a pair of long (20ft, 6m) wires that are not connected but are just coiled together.

I suspect the next thing to try would be a twisted pair.

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John Roberts {JR}:
I don't want to rain on your parade but many circuit designers have been burned by those proto-boards.

If you take one apart you notice that the adjacent terminals look like capacitor plates. Maybe only a few pF but I learned that the hard way with digital prototypes where a few pF pin to pin was enough to cause issues.

Maybe there's a class lesson in dissecting your proto board.   8)

JR

Jay Barracato:
No rain for me, that is the real life stuff I like to include.

Notice the separation between the two independent circuits. The only place close to adjacent pins are used is on the cap jumping the pin gap.

In practice, I rarely use adjacent pins except with chips, and I believe ( but don't quote me) that most of my stock is on the order of fF for capacitance between pins.

Of course, for teaching purposes, we are using TTL at 5 V which gives us a wider range of error tolerance, but I can't say I have seen any glitching on the stuff we have built in class.

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John Roberts {JR}:

--- Quote from: Jay Barracato on April 17, 2019, 06:52:47 am ---No rain for me, that is the real life stuff I like to include.

Notice the separation between the two independent circuits. The only place close to adjacent pins are used is on the cap jumping the pin gap.

In practice, I rarely use adjacent pins except with chips, and I believe ( but don't quote me) that most of my stock is on the order of fF for capacitance between pins.

Of course, for teaching purposes, we are using TTL at 5 V which gives us a wider range of error tolerance, but I can't say I have seen any glitching on the stuff we have built in class.

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--- End quote ---
It has been decades since this happened so I don't recall the exact circuit but very likely 5V logic and subtle timing errors caused by the unexpected inter lead C messing up a memory read/write.

Plugging in DIPs makes the pin to pin C unavoidable. I'm an old analog guy, so getting all the digital timing handshakes right was always a PIA... I very much prefer the modern embedded processors where most of that is handled internally so easier for an old analog guy to deal with.   

JR

PS: I haven't seen one of those proto boards for decades, let alone used one, not worth the unexpected gotcha's.

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