Here's what I've got. I mis-remembered when I posted and it's 60 degrees out on each end. It's +3 in the middle and +9 at 122 and 2880. I'm guessing your interface is responsible for the sharp drop off that you're seeing at the top. My straight through cable measurement is truly flat so this slope is all the qsys.
I did email qsc this AM and they are looking into it.
I'm wondering what the expected phase response of a system processor running straight through should be. I (perhaps naively) expected it would be flat except perhaps at the edges.
I look forward to what you hear from support...btw, support gave me great help understand the q-sys limiters...public thank you, QSC!
The screen I posted was at Smaart at 96kHz.
The one below includes the previous trace, and two taken at 48kHz, one sample apart.
The red phase trace is per Smaart's delay finder at 3.17ms, and I think matches what you got.
The darker green trace is manually ticking the delay finder down 1 sample to 3.15ms.
As you can see, the high end tail either fades up or down around zero.
Smart said +83degrees, and -65 at 20Khz. So a spread of almost 150 degrees for one sample timing change.
Which I think makes sense.
One wavelength at 20kHz has a period of 0.05ms. One sample is 0.021ms.
So one sample represents 360 * (.021/.05) degrees, or about 150 degrees as seen in the traces.
I think the "luck" of what the true timing is, places it right in the middle of samples at 48k,
and that is why 96k is more at zero...
That's just what I've come to on my own...looking forward to what QSC says...